1. Field of the Invention
The present invention relates to a data transmitting/receiving device and method of a multiprocessor system and, more particularly, to a device and method for transmitting and receiving data between processors in a multiprocessor system for improving the system performance.
2. Description of the Related Art
Generally, a multiprocessor system consists of a plurality of processors that transmit and receive data between one another. An example of such a multiprocessor system is the fiber loop carrier (FLC), which commonly is employed as an optical transmission device.
In the prior art, the processors of a multiprocessor system communicate with the CPU and with the various peripheral devices in accordance with a shared-bus or bus occupying method or through a dual port RAM. In a bus occupying method, coordination between several processors using a common data bus is accomplished by placing on standby all of the processors except one processor currently occupying the bus. The occupying processor reads data from or writes data to the SRAM. Upon release of the bus by the occupying processor, another processor can access the SRAM and read data stored there by the first processor, thereby realizing communication between the processors. This approach requires no special hardware components, but it fails to realize the computational potential of parallel processing because any processor's memory operation delays the memory operations of all the other processors.
Dual port RAM (DPRAM) architectures have offered an alternative to bus occupation by allowing simultaneous access by two adjacent processors to a memory unit interposed between them If each processor connects to one or more other processors through interposed DPRAMs, then data can be rapidly transferred from one processor to the next by means of the DPRAMs. Indeed, this interconnection method is usefully employed for high speed data communication in various contexts. When the subject system includes many processors, though, this solution becomes expensive because it requires a large number of DPRAMs, thereby increasing the manufacturing cost of the multiprocessor system.